In recent years, in response to demands from the market for smaller mobile devices, a system in which DRAMs and processor chips are stacked in the same package is being developed. In such system, since signal terminals that transmit data between the DRAMs and the processors are connected by wirings inside the package, it is difficult to inspect the DRAM chips directly through external terminals after sealed in the package. For this reason, such DRAMs need to be inspected for quality inspection before mounted on a package, that is, at the wafer level. In order to reduce costs for testing, the DRAM wafer inspection is carried out on 200 chips or more by simultaneously probing signal terminals from a memory tester. Thus, the number of signals assigned to each of the memory chips is limited by the total number of signal terminals of the memory tester. Meanwhile, in the system configuration of such mobile device, for better performance, the data input/output terminals of the DRAM is being extended to ×16, ×32, and ×64 to increase the data transmission rate. Thus, conventionally, DRAMs used for such purposes have a test mode, aiming to realize a wafer inspection with a small number of signal terminals and a certain number of data input/output terminals even when measuring many chips simultaneously.
Patent Document 1 discloses a double-data-rate synchronous dynamic random access memory (hereinafter referred to as DDR-SDRAM) that conducts a test with 8 input/output terminals (DQ0, DQ4, DQ8, DQ12, DQ16, DQ20, DQ24, and DQ28) among 32 data input/output terminals (DQ0 to DQ31) (see FIGS. 21 to 23, FIGS. 27 and 28, and paragraphs 0005 to 0009, 0172 to 0189, and 0207 to 0221 of Patent Document 1; or FIGS. 21 to 23, FIGS. 27 and 28, and column 1 line 40 to column 2 line 8, column 19 line 46 to column 21 line 5, and column 22 line 62 to column 24 line 7 of U.S. Pat. No. 6,324,118).
Patent Document 1: Japanese Patent Kokai Publication No. JP-P2000-76853A, which corresponds to U.S. Pat. No. 6,324,118